TMS320C5517AZCH20

Fixed-Point Digital Signal Processor

1 Device Overview

1.1 Features

• CORE:– High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor

• 13.33- to 5-ns Instruction Cycle Time

• 75- to 200-MHz Clock Rate

• OneorTwoInstructions Executed per Cycle

• Dual Multiply-and-Accumulate Units (Up to 450 Million Multiply-Accumulates per Second [MMACS])

• TwoArithmetic and Logic Units (ALUs)

• Three Internal Data or Operand Read Buses and Two Write Buses

• Software-Compatible with C55x Devices

• Industrial Temperature Devices Available

– 320KB of Zero-Wait State On-Chip RAM:

• 64KBof Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit

• 256KB of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit

– 128KB of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)

– Tightly Coupled FFT Hardware Accelerator

• PERIPHERAL:

– OneUniversal Host-Port Interface (UHPI) with 16-Bit Muxed Address or Data Bus

– Master and Slave Multichannel Serial Ports Interface (McSPI) with Three Chip Selects

– Master and Slave Multichannel Buffered Serial Ports Interface (McBSP)

– 16- and 8-Bit External Memory Interface (EMIF) with Glueless Interface to:

• 8-or 16-Bit NAND Flash, 1- or 4-Bit ECC • 8-and 16-Bit NOR Flash

• Asynchronous Static RAM (SRAM)

• SDRAMormSDRAM(1.8, 2.75, and 3.3 V)

– 3.84375M x 16-Bit Maximum Addressable External Memory Space (SDRAM or mSDRAM)

– Universal Asynchronous Receiver/Transmitter (UART)

– Device USB Port with Integrated 2.0 High Speed PHY that Supports:

• USB2.0 Full- and High-Speed Devices

– Direct Memory Access (DMA) Controller

• Four DMAwith Four Channels Each

– Three 32-Bit General-Purpose (GP) Timers

• OneSelectable as a Watchdog or GP

• Clocking Options, Including External General-Purpose I/O (GPIO) Clock Input

– TwoMultiMedia Card and Secure Digital (eMMC, MMC, and SD) Interfaces

– Serial Port Interface (SPI) with Four Chip Selects

– Master and Slave Inter-Integrated Circuit (I2C Bus)

– Three Inter-IC Sound (I2S Bus) Modules for Data Transport

– 10-Bit 4-Input Successive Approximation (SAR) ADC

– IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

– Upto 26 GPIO Pins (Multiplexed with Other Functions)

• POWER:

– Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB

– Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO

– 1.05-V Core, 1.8-, 2.75-, or 3.3-V I/Os

– 1.3-V Core, 1.8-, 2.75-, or 3.3-V I/Os

– 1.4-V Core, 1.8-, 2.75-, or 3.3-V I/Os

• CLOCK:

– Real-Time Clock (RTC) with Crystal Input, Separate Clock Domain, and Power Supply

– Software-Programmable Phase-Locked Loop (PLL) Clock Generator

• BOOTLOADER:

– On-Chip ROM Bootloader

• EachPeripheral Supports Unencrypted Booting

• PACKAGE:

– 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix), 0.65-mm Pitch

1.2 Applications

• Digital Two-Way Radios

• Low-Power Analytics Applications (such as Speech Recognition, Vision Sensing, and Fingerprint Biometrics)

• Voice Applications (such as Voice Recorders, Hands-Free Kits, and Voice-Enhancement Subsystems)

• Audio Devices (such as Echo-Cancellation Headphones and Speakerphones or Wireless Headsets and Microphones)

• Portable Medical Devices

1.3 Description

This device is a member of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.

The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32 bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.

Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).

Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.