ATSAMA5D29-TA100-CN

SAMA5D29 TA100 SIP,BGA,EXT TEMP

Description

The SAMA5D29 is a high-performance, ultra-low-power Arm Cortex-A5 CPU-based embedded microprocessor (MPU) running up to 500 MHz, with support for multiple memories such as DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3, QSPI and e.MMC Flash, and SLC/MLC parallel NAND Flash memory up to 32-bit ECC. It integrates the Arm Neon™ SIMD engine for accelerated multimedia and signal processing, a configurable 128-Kbyte L2 cache and a floating point unit (FPU) for high-precision computing. The device features an advanced user interface and connectivity peripherals. Advanced security is provided by powerful cryptographic accelerators, by the Arm TrustZone® technology securing access to memories and sensitive peripherals, and by several hardware features that safeguard memory content, authenticate software, detect physical attacks and prevent information leakage during code execution.

The SAMA5D29 features an internal multilayer bus architecture associated with 2 x 16 DMA channels and dedicated DMAs for the communication and interface peripherals required to ensure uninterrupted data transfers with minimal processor overhead.

The comprehensive peripheral set includes an LCD TFT controller with overlays for hardware-accelerated image composition, an image sensor controller, audio support through I2S, SSC, a stereo Class D amplifier and a digital microphone. Connectivity peripherals include a 10/100 EMAC with IEEE®1588 support, USBs, two ISO-compliant CAN-FD interfaces, FLEXCOMs, UARTs, SPIs and two QSPIs, SDIO/SD/e.MMCs, and TWIs/I2C.

Protection of code and data is provided by automatic scrambling of memories and an Integrity Check Monitor (ICM) to detect any modification of the memory contents. The SAMA5D29 also supports execution of encrypted code (QSPI or one portion of the DDR) with an “on-the-fly” encryption-decryption process.

With its secure design architecture, cryptographic acceleration engines, and secure bootloader, the SAMA5D29 is the ideal solution for IoT and industrial applications requiring device authentication, anti-cloning, data protection and secure communication.

The SAMA5D29 features three software-selectable low-power modes: Idle, Ultra-Low-Power and Backup.

In Idle mode, the processor is stopped while all other functions can be kept running.

In Ultra-Low-Power mode 0, the processor is stopped while all other functions are clocked at 512 Hz and interrupts or peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up.

In Ultra-Low-Power mode 1, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up.

In Backup mode, RTC and wake-up logic are active. The Backup mode can be extended to feature DDR in Self-refresh mode.

The SAMA5D29 also includes an event system that allows peripherals to receive, react to and send events in Active and Idle modes without processor intervention.

The SAMA5D29 is delivered with AutoSAR MCAL libraries, as well as a free Linux® distribution, EGT, Harmony and MPLAB®-X support.

The SAMA5D29 is AEC-Q100 grade 2 qualified.

Features

• Arm Cortex-A5 Core

– Armv7-A architecture

– Arm TrustZone

– NEON™ Media Processing Engine

– Up to 500 MHz

– ETM/ETB 8 Kbyte

• Memory Architecture

– Memory Management Unit (MMU)

– 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache

– 128-Kbyte L2 cache configurable to be used as an internal SRAM

– One 128-Kbyte scrambled internal SRAM

– One 160-Kbyte internal ROM

• 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader

• 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table

– High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting up to 512 Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) / LPDDR1/ LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path

– 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)

• System Running up to 166 MHz in Typical Conditions

– Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT), independent Watchdog Timer (WDT) and secure Real-Time Clock (RTC) with clock calibration

– One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for high-speed USB

– Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)

– Internal low-power 12 MHz RC and 32 kHz typical RC oscillator

– Selectable 32.768 Hz low-power crystal oscillator and 8 to 24 MHz crystal oscillator

– 51 DMA channels including two 16-channel 64-bit Central DMA Controllers

– One Advanced Interrupt Controller (AIC)

– One Secure Advanced Interrupt Controller (SAIC)

– Three programmable external clock signa

• Low-Power Modes

– Ultra-low-power mode with fast wake-up capability

– Low-power Backup mode with 5-Kbyte SRAM and asynchronous partial wake-up features

• Wake up from up to nine wake-up pins, UART reception, analog comparison

• Fast wake-up capability

• Extended Backup mode with DDR in Self-Refresh mode

• Peripherals

– LCD TFT controller (LCDC) up to 1024x768 or 1280x768 (still image). Four overlays, rotation, post processing and alpha blending, 24-bit parallel RGB interface

– ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 Mpixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface

– Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier (CLASSD)

– One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)

– One Pulse Density Modulation Interface Controller (PDMIC)

– One USB device high-speed port (UDPHS) and one USB host high-speed port or two USB host high-speed ports (UHPHS)

– One USB host high-speed port with a High-Speed Inter-Chip (HSIC) interface

– One 10/100 Ethernet MAC (GMAC)

• Energy efficiency support (IEEE® 802.3az standard)

• Ethernet AVB support with IEEE802.1AS timestamping

• IEEE802.1Qav credit-based traffic-shaping hardware support

• IEEE1588 Precision Time Protocol (PTP)

– Two high-speed memory card hosts:

• SDMMC0: SD 3.0, eMMC 4.51, 8 bits

• SDMMC1: SD 2.0, eMMC 4.41, 4 bits only

– Two host/client Serial Peripheral Interfaces (SPI)

– Two Quad Serial Peripheral Interfaces (QSPI)

– Five FLEXCOMs (USART, SPI and TWI)

– Five UARTs

– Two host CAN-FD (MCAN) controllers with SRAM-based mailboxes, time- and event-triggered transmission, and 32-bit Time Stamping Unit (TSU)

– One Rx only UART in backup area (RXLP)

– One Analog Comparator Controller (ACC) in backup area

– Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS

– One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller

– Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes

– One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with resistive touchscreen capability

• Safety

– Zero-power Power-on Reset (POR) cells

– Main crystal clock failure detector

– Write-protected registers

– Integrity Check Monitor (ICM) based on SHA256

– Memory Management Unit (MMU)

– Independent watchdog

• Security

– 5 Kbytes of internal scrambled SRAM:

• 1 Kbyte non-erasable on tamper detection

• 4 Kbytes erasable on tamper detection

– 256 bits of scrambled and erasable registers

– Up to eight tamper pins for static or dynamic intrusion detections(1)

– Secure Bootloader(2)

– On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB)

– RTC including timestamping on security intrusions

– Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)

Notes: 

1. For information on dynamic tamper protection (PIOBU), refer to the document SAMA5D2 External Tamper Protections. Contact a Microchip Sales Representative for details.

2. For information on secure boot strategies, refer to the document SAMA5D2 Secure Boot Strategy. Contact a Microchip Sales Representative for details.

• Hardware Cryptography

– SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2

– AES: 256-, 192-, 128-bit key algorithms, compliant with FIPS PUB 197

– TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3

– True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3

• Up to 128 I/Os

– Fully programmable through set/clear registers– Multiplexing of up to eight peripheral functions per I/O line

– Each I/O line can be assigned to a peripheral or used as a general-purpose I/O

– The PIO controller features a synchronous output providing up to 32 bits of data output in one write operation

• Available in a 289-ball LFBGA, 14 x 14 mm Body, 0.8 mm Pitch Package

1. Configuration Summary Table 1-1. Configuration Summary

2. Block Diagram