ATMEGA64A-AU

IC MCU 8BIT 64KB FLASH 64TQFP

Introduction

The Atmel' ATmega64A is a low-power CMOS 8-bit microcontroller basedon the AVR" enhanced RlSC architecture.By executing powerful instructionsin a single clock cycle, the ATmega64A achieves throughputs close to1MlPS per MHz. This empowers system designer to optimize the device forpower consumption versus processing speed.

Features

High-performance, Low-power Atmel AVR 8-bit MicrocontrollerAdvanced RlSC Architecture

130 Powerful Instructions -Most Single-clock Cycle Execution32 x 8 General Purpose Working Registers + Peripheral ControlRegisters

Fully Static OperationUp to 16MIPS Throughput at 16MHzOn-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments64Kbytes of In-System Self-programmable Flash programmemory

2Kbytes EEPROMM

4Kbytes Interal SRAMWrite/Erase cycles: 10,000 Flash/100,000 EEPROMData retention: 20 years at 85°C/100 years at 25°C(1)Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation

Up to 64 Kbytes Optional External Memory SpaceProgramming Lock for Software Security

SPI Interface for In-System ProgrammingJTAG (lEEE std.1149.1 Compliant) Interface

Boundary-scan Capabilities According to the JTAG Standard

Extensive On-chip Debug Support

Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG InterfaceAtmel QTouch® library support

Capacitive touch buttons,sliders and wheels

Atmel QTouch and QMatrix acquisition

Up to 64 sense channels

Peripheral Features

Two 8-bit Timer/Counters with Separate Prescalers and Compare ModesTwo Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and CaptureMode

Real Time Counter with Separate Oscillator

Two 8-bit PWM Channels

6 PWM Channels with Programmable Resolution from 1 to 16 BitsOutput Compare Modulator8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain at 1x,10x, or 200xByte-oriented Two-wire Serial Interface

Dual Programmable Serial USARTs

Master/Slave SPl Serial Interface

Programmable Watchdog Timer with On-chip OscillatorOn-chip Analog ComparatorSpecial Microcontroller Features

Power-on Reset and Programmable Brown-out Detection

Internal Calibrated RC Oscillator

External and Internal Interrupt Sources

Six Sleep Modes: ldle, ADC Noise Reduction, Power-save, Power-down, Standby, andExtended Standby

Software Selectable Clock Frequency

ATmega103 Compatibility Mode Selected by a Fuse

Global Pull-up Disable

l/O and Packages

53 Programmable l/O Lines

64-lead TQFP and 64-pad QFN/MLF

Operating Voltages

2.7-5.5V

Speed Grades

0-16MHz

Description

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers tobe accessed in one single instruction executed in one clock cycle. The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read.While- Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose l/0 lines, 32 generapurpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modesand PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optionaldiferential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator.an SPl serial port, lEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chipDebug system and programming, and six software selectable power saving modes. The ldle mode stopsthe CPU while allowing the SRAM, Timer/Counters, SPl port, and interrupt system to continuefunctioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling allother chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronoustimer continues to run, allowing the user to maintain a timer base while the rest of the device is sleepingThe ADC Noise Reduction mode stops the CPU and all l/0 modules except asynchronous timer andADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonatorOscillator is running while the rest of the device is sleeping. This allows very fast start-up combined withlow power consumption. In Extended Standby mode, both the main Oscilator and the asynchronous timercontinue to run.

The device is manufactured using Atmel's high-density non-volatile memory technology. The On-chip ISPFlash allows the program memory to be reprogrammed In-System through an SPl serial interface, by aconventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR coreThe Boot Program can use any interface to download the Application Program in the Application Flashmemory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RlSC CPU with In-SystemSelf-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller thatprovides a highly-flexible and cost-effective solution to many embedded control applications.The ATmega64A AVR is supported with a full suite of program and system development tools including: Ccompilers, macro assemblers, proaram debugger/simulators, in-circuit emulators, and evaluation kits

Block Diagram

Figure 4-1 Block Diagram